Excess 3 to bcd code converter

ABSTRACT

An excess 3 to binary coded decimal converter is described which includes a plurality of EXCLUSIVE-OR gates and means for coupling the EXCLUSIVE-OR gates so that in response to excess 3 coded input signals, the EXCLUSIVE-OR gates provide binary coded decimal output signals.

United States Patent Spani [52] U.S. Cl. ..235/155, 340/347 DD [5 1] Int. Cl. ..H04l 3/00 [58] Field of Search ..235/155, 92; 340/347 DD [56] 1 References Cited UNITED STATES PATENTS 2,877,447 Kenrich ..235/155 Winkler ..235/155 [4 1 Dec. 19,1972

OTHER PUBLICATIONS Frim & Miller, Here Are More Digital Converters Electronic Design 25, Dec. 6, 1969 pg. 87.

Primary Examiner-Daryl W. Cook Assistant Examiner-Jeremiah Glassman Attorney-W. H. J. Kline and Raymond L. Owens [5 7 ABSTRACT An excess 3 to binary coded decimal converter is described whichincludes a plurality of EXCLUSIVE- OR gates and means for coupling the EXCLUSIVE- OR gates so that in response to excess 3 coded input signals, the EXCLUSIVE-OR gates provide binary coded decimal output signals.

6 Claims, 1 Drawing Figure PAIENTED E 1 I 3.706. 878

:2 of]? T- 0] WAYNE SPAN! INVENTOR.

A T TORNE YS 1 EXCESS 3 TO BCD CODE CONVERTER c oss REFERENCE To RELATED APPLICATIONS Reference is made to commonly assigned copending U.S. Pat. application, Ser. No. 124,683, entitled BCD to Excess 3 Code Converter" filed contemporaneously herewith in the name of Wayne Spani.

BACKGROUND OF THE INVENTION SUMMARY oF THE INVENTION In the disclosed embodiment of the invention, an excess 3'to BCD converter includes a plurality of EX- CLUSIVE-OR gates adapted-to receive as inputs excess 3 coded input signals 1,, I 1 and 1 and circuit means for coupling the EXCLUSIVE-OR gates sothat they provide BCD output signals 0,, and O in accordance with the following Boolean relationships between the input and the output signals.

s 2 s I LU; A feature of the invention is that excess 3 to BCD code conversion is accomplished with substantial I savings in the number of logic gates used. Other objects and advantages will become more apparent from the detailed description of a preferred embodiment.

BRIEF DESCRIPTION OF THE DRAWING In the detailed description of the preferred embodiment of the invention presented below, reference is made to the accompanying drawing which depicts a a block diagram of an excess 3 to BCD code converters in accordance with the invention. The symbols for the logic components shown in the drawing are in accordance with the American Standard Graphical Symbols for Logical Diagrams (ASA Y 32.14-1962).

DESCRIPTION OF THE PREFERRED EMBODIMENT To facilitate an understanding of the present invention, the BCD and excess 3 codes will be first briefly reviewed in conjunction with Table l and Table II which show for the decimal digits 0 -9 (left column) the BCD and excess 3 equivalent respectively.

TABLE I Binary Coded Decimal Code Decimal Digit 0. O O, O,

TABLE II ExcessSCode Decimal Digit 1. I I, I

- ment of a decimal digit expressed in excess 3 code may be obtained by complimenting each particular individual bit. For example, for the decimal digit 1, the

excess 3 code representation is the number 0100' whose compliment on an individual bit basis is 1011 which in the excess 3 code has a decimal equivalent of 8.

Referring now to the drawing, there is shown an excess 3 to BCD code converter having a plurality of input terminals for a plurality of excess 3 input signals 1,, 1 I and 1 respectively and a plurality of output terminals for a plurality of BCD output signals 0 O O and 0 respectively. The converter 10 includes a plurality of EXCLUSIVE-OR gates 12, 14, 16,- and 18.

Boolean Algebra is well known to those skilled in the art to express the output signals of combinational logic systems in terms of its input signals. Upon analysis using Boolean Algebra (see Hill and Peterson, Introduction to Switching Theory Logic Design, 1968), the disclosed code converter solves the four following Boolean equations which present a mathematical model of the converter 10 and convert the excess 3 code of Table II into the BCD code of Table 1.

Equations: 1.O,=T;

Again referring specifically to the drawing, EXCLU- SIVE-OR gate 12 is responsive to only the input signal I and thus provides an inverter function. The gate 12 provides the output signal 0 to satisfy equation 1. The EXCLUSIVE-OR gate 12 could be replaced by a signal inverter and still solve Equation 1. The input signal I is also provided as an input to the EXCLUSIVE-0R gate 14 and a NAND gate 20. The EXCLUSIVE-OR gate 14 also receives input signal I, and provides an output signal 0, which satisfies Equation 2. NAND gate 20 also receives the signal I, as an input and produces a first reference signal having the Boolean representation T1: which is provided as an input to the EXCLUSIVE- OR gate 16. The EXCLUSIVE-OR gate 16 also is responsive to the input signal I and produces an output signal 0 which satisfies equation3. The first reference signal from the NAND gate 20 is also directly coupled to the input of an AND gate 24. An inverter 22 receives the input signal 1 and provides the inverter signal I as an input to the AND gate 24. The AND gate 24 effected'withinthe spirit and scope of the invention.

. 3 develops a second reference signal T mwhich is provided as an input to the EXCLUSIVE-OR gate 18. The EXCLUSIVE-OR gate 18 in response to the output of the AND gate 24 and the input signal I produces the output signal which solves equation 4.

Although the-disclosed embodiment of the present invention uses a plurality of EXCLUSIVE-QR gates, it will be understood to those skilled in the art that the EXCLUSIVE-QR function may also be realized by the correct selection of a number of other combinationv of gates. I The invention has been described in detail with particular reference to a preferred embodiment, but it will be understood-that variations and modifications can be- I; claim:

1. In an ex c'essf3 to BCD code converter for converting excess 3 input signals I 1 .1 and I to BCD output signalso 'O O and O the.combinationcomprising: e

a. a plurality of EXCLUSIVE-OR means; I

b. circuit means defining a plurality of input ,ter- I minals for the excess 3 input signals I ,I I and I and a plurality of output terminals for the BCD output terminals 0,; 0 ,0 and Q and c. means for coupling said EXCLUSIVE-OR means to said terminals to establish the following Boolean relationships between the input signals and output signals: 1.0 I 2. ()2 =12 11 2. In an excess 3 to BCD code converter for converting excess 3 input signals I 1,, I and I to BCD output signals 0 0 O and 0 the combination comprising:

a. at least threeEXCLUSIVE-OR gates;

b. a plurality of input terminals for the excess 3 input signals 1,, I I and I and a plurality of output terminals for. the BCD output terminals 0 O O andO and I c. means coupling said EXCLUSIVE-OR means to said terminals to satisfy the following Boolean relationships between the input signals and; output 4 =Ia III; 3. In an excess 3 providing the 0, signal; r b. first EXCLUSIVE-OR gate means responsive to the and I, signals for 'providing'the 0, signal; 0; means responsive to the I and I, signals for providing a firstreferencesignal; d. second EXCLUSIVE-OR gate means responsive to the I signal and said first reference signal for I second reference signal providing means comprises;

a. an inverter responsive to the I -signal to provide an inverted I signal; and

b. an AND gate responsive to said first reference said to BCD code converter for conv'erting excess 3 input signals I Inand I, to BCD output signals 0 0,, O and 0 the combination comprisingzf a. inverting means responsive to the I, signal for 

1. In an excess 3 to BCD code converter for converting excess 3 input signals I1, I2, I4, and I8 to BCD output signals O1, O2, O4, and O8, the combination comprising: a. a plurality of EXCLUSIVE-OR means; b. circuit means defining a plurality of input terminals for the excess 3 input signals I1, I2, I4, and I8 and a plurality of output terminals for the BCD output terminals O1, O2, O4, and O8; and c. means for coupling said EXCLUSIVE-OR means to said terminals to establish the following Boolean relationships between the input signals and output signals:
 1. O1 I1
 2. O2 I2 phi I1
 2. In an excess 3 to BCD code converter for converting excess 3 input signals I1, I2, I4, and I8 to BCD output signals O1, O2, O4, and O8, the combination comprising: a. at least three EXCLUSIVE-OR gates; b. a plurality of input terminals for the excess 3 input signals I1, I2, I4, and I8 and a plurality of output terminals for the BCD output terminals O1, O2, O4, and O8; and c. means coupling said EXCLUSIVE-OR means to said terminals to satisfy the following Boolean relationships between the input signals and output signals:
 2. O2 I2 phi I1
 2. O2 I2 phi I1
 3. O4 I4 phi I1I2
 3. In an excess 3 to BCD code converter for converting excess 3 input signals I1, I2, I4, and I8 to BCD output signals O1, O2, O4, and O8, the combination comprising: a. inverting means responsive to the I1 signal for providing the O1 signal; b. first EXCLUSIVE-OR gate means responsive to the I1 and I2 signals for providing the O2 signal; c. means responsive to the I1 and I2 signals for providing a first reference signal; d. second EXCLUSIVE-OR gate means responsive to the I4 signal and said first reference signal for providing the O4 signal; e. means responsive to said first reference signal and said I4 signal for providing a second reference signal; and f. third EXCLUSIVE-OR gate means responsive to said second reference signal and the I8 signal for providing the O8 signal.
 3. O4 I4 phi I1I2
 3. O4 I4 phi I1I2
 4. O8 I8 phi I4 I1I2
 4. O8 I8 phi I4 I1I2
 4. The invention as set forth in claim 3 wherein said inverting means comprises an EXCLUSIVE-OR gate.
 4. O8 I8 phi I4 I1I2
 5. The invention as set forth in claim 3 wherein said first reference signal means comprises a NAND gate.
 6. The invention as set forth in claim 5 wherein said second reference signal providing means comprises; a. an inverter responsive to the I4 signal to provide an inverted I4 signal; and b. an AND gate responsive to said first reference signal and said inverted I4 signal to provide said second reference signal. 